XC18V01SOG20C

Product Summary

Xilinx introduces the XC18V01SOG20C in-system programmable configuration PROM. Devices in this 3.3V family include a 4-megabit, a 2-megabit, a 1-megabit, and a 512-kilobit PROM that provide an easy-touse, cost-effective method for reprogramming and storing Xilinx FPGA configuration bitstreams. When the XC18V01SOG20C is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. New data is available a short access time after each rising clock edge. The XC18V01SOG20C generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the XC18V01SOG20C are clocked by an external clock.

Parametrics

XC18V01SOG20C absolute maximum ratings: (1)VCCINT/VCCO Supply voltage relative to GND: -0.5 to +4.0 V; (2)VIN Input voltage with respect to GND: -0.5 to +5.5 V; (3)VTS Voltage applied to high-Z output: -0.5 to +5.5 V; (4)TSTG Storage temperature (ambient): -65 to +150 ℃; (5)TJ Junction temperature: +125 ℃.

Features

XC18V01SOG20C features: (1)In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAs; (2)Endurance of 20,000 Program/Erase Cycles; (3)Program/Erase Over Full Industrial Voltage and Temperature Range (-40℃ to +85℃); (4)IEEE Std 1149.1 Boundary-Scan (JTAG) Support; (5)JTAG Command Initiation of Standard FPGA Configuration; (6)Simple Interface to the FPGA; (7)Cascadable for Storing Longer or Multiple Bitstreams; (8)Low-Power Advanced CMOS FLASH Process; (9)Dual Configuration Modes; (10)Serial Slow/Fast Configuration (up to 33 MHz); (11)Parallel (up to 264 Mb/s at 33 MHz); (12)5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals; (13)3.3V or 2.5V Output Capability; (14)Design Support Using the Xilinx ISEFoundationSoftware Packages; (15)Available in PC20, SO20, PC44, and VQ44 Packages; (16)Lead-Free (Pb-Free) Packaging.

Diagrams